Job Description

JD:

KEY RESPONSIBILITIES:

Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.

Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.

Develop and execute comprehensive verification plans, including testbenches and test cases.

Collaborate with design, architecture, and software teams to define and implement verification strategies.

Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.

Mentor and guide junior engineers, fostering a collaborative and innovative team environment.

PREFERRED EXPERIENCE:

10+ years of senior Pre-silicon verification engineer with PCIE physical, link layer experience in typical networking application products.

Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.

Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.

Require familiarity with verification management tools.

Prior years of experience in pre-silicon validation within the semiconductor industry

Demonstrated ability to grasp new technical concepts quickly

Hardware description languages (e.g. Verilog)

Experience with IP/System level bring-up, SOC debug techniques and methodologies

Strong understanding of BIOS, OS, and driver-level interactions and common failure points

Strong analytical/problem solving skills and pronounced attention to details

Excellent written and verbal communication skills

Self-starter, strong collaborator, and able to independently drive tasks to completion

Strong organizational skills and ability to handle multiple issues at the same time

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